The present invention relates to a differential ring oscillator stage, comprising differential delay means having a first input and an inverse second input and a first output and an inverse second output, a first output buffer means having its input connected to the first output of said delay means, and a second output buffer means having its input connected to the second output of said delay means.
Ring oscillators are widely known in the field of integrated circuit manufacture and usually comprise simple inverting logic circuits as stages. The current output of each stage takes a certain time to charge or discharge an input capacitance of the following stage to a threshold voltage. The stages are connected in series to form a cascade loop, so that at a certain frequency a 180xc2x0 phase shift is imparted to signals passing around the loop. Provided the loop gain is large enough, the signals soon become non-linear resulting in square-wave oscillations which can be used for a variety of purposes, in particular for digital signal processing.
In metal-oxide-semiconductor (MOS) integrated circuits, ring oscillators are commonly used to drive charge pump circuits. In particular, ring oscillators are provided in BiCMOS or Bipolar and also in pure CMOS circuits. A preferred application of ring oscillators is the provision in data and clock recovery circuits or in PLL circuits.
U.S. Pat. No. 5,412,349 A discloses a PLL based deskewed clock generator. The clock generator comprises a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator from which the internal clock is generated. The voltage controlled oscillator is based on a five stage ring oscillator where each stage is a differential current controlled delay cell. The delay through each cell is a function of the tail current through a p-channel differential source coupled pair, the differential voltage swing between the first output and the inverse second output, and the capacitive load on the first and second outputs. The voltage swing in the delay cell is held constant and independent of the supply voltage by utilizing voltage controlled resisters in the delay stage, a power supply insensitive voltage swing reference generator, a feedback replica biasing circuit and a voltage to current converter. The differential signal outputted form the ring oscillator is fed to a buffer amplifier which is implemented as a differential amplifier and converts the differential signal to a single ended highspeed clock signal.
U.S. Pat. No. 5,691,669 A discloses dual adjust current-controlled phase locked loop which is provided for a allowing multiple-gain frequency acquisition of a signal. The dual adjust current-controlled phase locked loop includes a phase detector responsive to a reference signal and a synthesized signal for producing a phase error signal, a controller responsive to the phase error signal for generating coarse and fine adjust control signals, and a dual adjust current-controlled oscillator responsive to the coarse and fine adjust control signals for adjusting the oscillating frequency of the synthesized signal. The dual adjust current-controlled oscillator includes a differential current-controlled ring oscillator comprising a series of delay elements. Each delay element includes a high gain circuit responsive to the coarse adjust control signal and a low gain circuit responsive to the fine adjust control signal.
In order to achieve a high oscillator frequency in the GHz range, an obvious choice would be to limit the number of stages to two. The oscillator frequency can be varied by changing the delay per stage and if one can ensure a fine and a coarse tuning mechanism, then the oscillator will have two tuning ports. In optical networking application for applications above 10 GB/s low phase noise is essential to recover the clock in a Data and Clock Recovery circuit (DCR) with the additional requirement that the oscillator should provide an oscillation frequency stable with temperature and process variations. For some applications with more than one Data rate, a large tuning range oscillator is required. The linearity of the oscillator is also important for the reason of keeping the loop bandwidth of the PLL constant for different tuning situations.
The first and second output buffer means defining the differential output buffer means are included in the differential ring oscillator stage in order to provide a level shifting operation and to minimize the loading effect of the next stage. Since the signals in question are digital signals and consist of a series of pulses, the waveform of such pulses should be rectangular and, consequently, their edges should be vertical. However, due to certain physical effects the leading edges need a certain time to rise and the trailing edges need a certain time to fall, so that in reality the waveform of the pulses is not rectangular, but trapezoidal. Such a deviation from the ideal case of a rectangular waveform is basically not a problem in case the zero-crossings are interesting only. However, in particular due to the currents of parasitic capacitances at the outputs, the waveform of the signal is not symmetrical, but becomes asymmetrical wherein the fall-time of the trailing edges are longer than the rise-time of the leading edges. This effect results in phase noise and jitter which is a big disadvantage since an exact detection of the zero-crossings is not possible. In particular, at large signal amplitudes the current at the outputs saturate which leads to a very high asymmetry of the waveform.
It is an object of the present invention to provide a differential ring oscillator stage having reduced phase noise and jitter.
In order to achieve this and other objects, in accordance with the present invention, there is provided a differential ring oscillator stage, comprising
differential delay means having a first input and an inverse second input and a first output and an inverse second output,
a first output buffer means having its input connected to the first output of said delay means, and
a second output buffer means having its input connected to the second output of said delay means,
further characterised by
a first controllable current source means which is connected to the output of said first output buffer means and controlled in accordance with the signal from said second output of said delay means, and
a second controllable current source means which is connected to the output of said second output buffer means and controlled in accordance with the signal from said first output of said delay means,
said controllable current source means supplying currents to the output of said output buffer means such that within the working range the waveform of the currents is essentially proportional to the waveform of the signal from the output of said delay means.
The construction of the present invention leads to the advantage that the fall-time of the trailing edges of the output signals from the output buffer means is shortened and adapted to the rise-time so that the fall-time is equal to the rise-time of the edges and the waveform of the output signal becomes symmetrical. This is achieved by that in each output buffer means additional current is generated by the controllable current source means in accordance with the inverse output signal from the delay means, respectively so as to shorten the fall-time of the trailing edge of the output signal from the output buffers. In other words, in each output buffer means the waveform of the trailing edge of its output signal is controlled by the leading edge of the inverse output signal from the delay means, respectively, so as to make the waveform of the trailing edge of the output signals from the output buffer means equal to the waveform of the leading edge of the inverse output signals from the delay means and, thus, to the waveform of the leading edge of the output signals from the output buffer means, accordingly. The currents flowing through the output buffer means cannot saturate. A further advantage over the prior art is that due to the construction of the present invention the output buffer means have a gain higher than 1.
After all, the present invention allows the provision of output signals with larger amplitudes and equal rise-fall-times which results in a reduction of the phase noise.
In a preferred embodiment of the present invention, the first controllable current source comprises a transistor, preferably a MOS transistor, having its base connected to said second output of said delay means, its emitter applied to a predetermined potential and its collector connected to the output of said first output buffer means. Moreover, the second controllable current source comprises a transistor, preferably a MOS transistor, having its base connected to said first output of said delay means, its emitter applied to a predetermined potential and its collector connected to the output of said second output buffer means, wherein said predetermined potential is preferably zero (ground). These embodiments provide a simple construction wherein the waveform of the output signals from the output buffers is still symmetrical if such transistors go into the linear region.